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Article: Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network

TitleLow-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network
Authors
KeywordsCell image classification
convolutional neural network (CNN)
field-programmable gate array (FPGA)
hardware architecture
low-latency inference
Issue Date2021
PublisherInstitute of Electrical and Electronics Engineers. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=72
Citation
IEEE Transactions on Neural Networks and Learning Systems, 2021, Epub 2021-01-12 How to Cite?
AbstractReal-time in situ image analytics impose stringent latency requirements on intelligent neural network inference operations. While conventional software-based implementations on the graphic processing unit (GPU)-accelerated platforms are flexible and have achieved very high inference throughput, they are not suitable for latency-sensitive applications where real-time feedback is needed. Here, we demonstrate that high-performance reconfigurable computing platforms based on field-programmable gate array (FPGA) processing can successfully bridge the gap between low-level hardware processing and high-level intelligent image analytics algorithm deployment within a unified system. The proposed design performs inference operations on a stream of individual images as they are produced and has a deeply pipelined hardware design that allows all layers of a quantized convolutional neural network (QCNN) to compute concurrently with partial image inputs. Using the case of label-free classification of human peripheral blood mononuclear cell (PBMC) subtypes as a proof-of-concept illustration, our system achieves an ultralow classification latency of 34.2 μs with over 95% end-to-end accuracy by using a QCNN, while the cells are imaged at throughput exceeding 29,200 cells/s. Our QCNN design is modular and is readily adaptable to other QCNNs with different latency and resource requirements.
DescriptionHybrid open access
Persistent Identifierhttp://hdl.handle.net/10722/296324
ISSN
2023 Impact Factor: 10.2
2023 SCImago Journal Rankings: 4.170
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorWANG, M-
dc.contributor.authorLEE, KCM-
dc.contributor.authorCHUNG, BMF-
dc.contributor.authorBogaraju, SV-
dc.contributor.authorNg, HC-
dc.contributor.authorWong, JS-
dc.contributor.authorShum, HC-
dc.contributor.authorTsia, KK-
dc.contributor.authorSo, HKH-
dc.date.accessioned2021-02-22T04:53:41Z-
dc.date.available2021-02-22T04:53:41Z-
dc.date.issued2021-
dc.identifier.citationIEEE Transactions on Neural Networks and Learning Systems, 2021, Epub 2021-01-12-
dc.identifier.issn2162-237X-
dc.identifier.urihttp://hdl.handle.net/10722/296324-
dc.descriptionHybrid open access-
dc.description.abstractReal-time in situ image analytics impose stringent latency requirements on intelligent neural network inference operations. While conventional software-based implementations on the graphic processing unit (GPU)-accelerated platforms are flexible and have achieved very high inference throughput, they are not suitable for latency-sensitive applications where real-time feedback is needed. Here, we demonstrate that high-performance reconfigurable computing platforms based on field-programmable gate array (FPGA) processing can successfully bridge the gap between low-level hardware processing and high-level intelligent image analytics algorithm deployment within a unified system. The proposed design performs inference operations on a stream of individual images as they are produced and has a deeply pipelined hardware design that allows all layers of a quantized convolutional neural network (QCNN) to compute concurrently with partial image inputs. Using the case of label-free classification of human peripheral blood mononuclear cell (PBMC) subtypes as a proof-of-concept illustration, our system achieves an ultralow classification latency of 34.2 μs with over 95% end-to-end accuracy by using a QCNN, while the cells are imaged at throughput exceeding 29,200 cells/s. Our QCNN design is modular and is readily adaptable to other QCNNs with different latency and resource requirements.-
dc.languageeng-
dc.publisherInstitute of Electrical and Electronics Engineers. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=72-
dc.relation.ispartofIEEE Transactions on Neural Networks and Learning Systems-
dc.rightsIEEE Transactions on Neural Networks and Learning Systems. Copyright © Institute of Electrical and Electronics Engineers.-
dc.rights©2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.rightsThis work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.-
dc.subjectCell image classification-
dc.subjectconvolutional neural network (CNN)-
dc.subjectfield-programmable gate array (FPGA)-
dc.subjecthardware architecture-
dc.subjectlow-latency inference-
dc.titleLow-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network-
dc.typeArticle-
dc.identifier.emailWong, JS: jsjwong@hku.hk-
dc.identifier.emailShum, HC: ashum@hku.hk-
dc.identifier.emailTsia, KK: tsia@hku.hk-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authorityShum, HC=rp01439-
dc.identifier.authorityTsia, KK=rp01389-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/TNNLS.2020.3046452-
dc.identifier.pmid33434136-
dc.identifier.scopuseid_2-s2.0-85099543895-
dc.identifier.hkuros321305-
dc.identifier.volumeEpub 2021-01-12-
dc.identifier.isiWOS:000733493900001-
dc.publisher.placeUnited States-

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