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Article: Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS2

TitleStatistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS<inf>2</inf>
Authors
Keywordsfield-effect transistors
Monolayer TMD materials
statistical study
ultrascaled dielectric
ultrashort channel length
WS 2
Issue Date2022
Citation
ACS Nano, 2022, v. 16, n. 9, p. 14942-14950 How to Cite?
AbstractScaling of monolayer transition metal dichalcogenide (TMD) field-effect transistors (FETs) is an important step toward evaluating the application space of TMD materials. Although some work on ultrashort channel monolayer (ML) TMD FETs has been published, there exist no comprehensive studies that assess their performance in a statistically relevant manner, providing critical insights into the impact of the device geometry. Part of the reason for the absence of such a study is the substantial variability of TMD devices when processes are not carefully controlled. In this work, we show a statistical study of ultrashort channel double-gated ML WS2FETs exhibiting excellent device performance and limited device-to-device variations. From a detailed analysis of cross-sectional scanning transmission electron microscopy (STEM) images and careful technology computer aided design (TCAD) simulations, we evaluated, in particular, an unexpected deterioration of the subthreshold characteristics for our shortest devices. Two potential candidates for the observed behavior were identified, i.e., buckling of the TMD on the substrate and loss of gate control due to the source geometry and the high-k dielectric between the metal gate and the metal source electrode.
Persistent Identifierhttp://hdl.handle.net/10722/335424
ISSN
2023 Impact Factor: 15.8
2023 SCImago Journal Rankings: 4.593
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorSun, Zheng-
dc.contributor.authorPang, Chin Sheng-
dc.contributor.authorWu, Peng-
dc.contributor.authorHung, Terry Y.T.-
dc.contributor.authorLi, Ming Yang-
dc.contributor.authorLiew, San Lin-
dc.contributor.authorCheng, Chao Ching-
dc.contributor.authorWang, Han-
dc.contributor.authorWong, H. S.Philip-
dc.contributor.authorLi, Lain Jong-
dc.contributor.authorRadu, Iuliana-
dc.contributor.authorChen, Zhihong-
dc.contributor.authorAppenzeller, Joerg-
dc.date.accessioned2023-11-17T08:25:47Z-
dc.date.available2023-11-17T08:25:47Z-
dc.date.issued2022-
dc.identifier.citationACS Nano, 2022, v. 16, n. 9, p. 14942-14950-
dc.identifier.issn1936-0851-
dc.identifier.urihttp://hdl.handle.net/10722/335424-
dc.description.abstractScaling of monolayer transition metal dichalcogenide (TMD) field-effect transistors (FETs) is an important step toward evaluating the application space of TMD materials. Although some work on ultrashort channel monolayer (ML) TMD FETs has been published, there exist no comprehensive studies that assess their performance in a statistically relevant manner, providing critical insights into the impact of the device geometry. Part of the reason for the absence of such a study is the substantial variability of TMD devices when processes are not carefully controlled. In this work, we show a statistical study of ultrashort channel double-gated ML WS2FETs exhibiting excellent device performance and limited device-to-device variations. From a detailed analysis of cross-sectional scanning transmission electron microscopy (STEM) images and careful technology computer aided design (TCAD) simulations, we evaluated, in particular, an unexpected deterioration of the subthreshold characteristics for our shortest devices. Two potential candidates for the observed behavior were identified, i.e., buckling of the TMD on the substrate and loss of gate control due to the source geometry and the high-k dielectric between the metal gate and the metal source electrode.-
dc.languageeng-
dc.relation.ispartofACS Nano-
dc.subjectfield-effect transistors-
dc.subjectMonolayer TMD materials-
dc.subjectstatistical study-
dc.subjectultrascaled dielectric-
dc.subjectultrashort channel length-
dc.subjectWS 2-
dc.titleStatistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS<inf>2</inf>-
dc.typeArticle-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1021/acsnano.2c05902-
dc.identifier.pmid36094410-
dc.identifier.scopuseid_2-s2.0-85139228486-
dc.identifier.volume16-
dc.identifier.issue9-
dc.identifier.spage14942-
dc.identifier.epage14950-
dc.identifier.eissn1936-086X-
dc.identifier.isiWOS:000859108900001-

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