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Conference Paper: Building high performance transistors on carbon nanotube channel

TitleBuilding high performance transistors on carbon nanotube channel
Authors
Keywords1D
2D
CMOS
CNT
low-dimensional material
Issue Date2023
Citation
Digest of Technical Papers - Symposium on VLSI Technology, 2023, v. 2023-June How to Cite?
AbstractHigh-performance and scaled transistors on carbon nanotube (CNT) channel are enabled by the quality of device component modules. This paper advances each module by single-CNT control experiments reporting: (1) remarkable n-type contact resistance of 5.1 kΩ/CNT(20.4Ω-μm for 250 CNT/μm) at 20 nm contact length, (2) tunable N-and Pdoping of CNT with dielectric doping, (3) improvement in top-gate dielectric interface to CNT by channel cleaning, (4) demonstration of channel comprised of dense CNT array with reduced bundle density, and (5) analysis of CNT bandgap tradeoffs with variability control strategy. The first component-complete pMOS FET is demonstrated on high-density CNTs with up to 680 μA/μm at -0.7V VDS.
Persistent Identifierhttp://hdl.handle.net/10722/335476
ISSN
2023 SCImago Journal Rankings: 0.911

 

DC FieldValueLanguage
dc.contributor.authorPitner, Gregory-
dc.contributor.authorSafron, Nathaniel-
dc.contributor.authorChao, Tzu Ang-
dc.contributor.authorLi, Shengman-
dc.contributor.authorSu, Sheng Kai-
dc.contributor.authorZeevi, Gilad-
dc.contributor.authorLin, Qing-
dc.contributor.authorChiu, Hsin Yuan-
dc.contributor.authorPasslack, Matthias-
dc.contributor.authorZhang, Zichen-
dc.contributor.authorSathaiya, D. Mahaveer-
dc.contributor.authorWei, Aslan-
dc.contributor.authorGilardi, Carlo-
dc.contributor.authorChen, Edward-
dc.contributor.authorLiew, San Lin-
dc.contributor.authorHou, Vincent D.H.-
dc.contributor.authorWu, Chung Wei-
dc.contributor.authorWu, Jeff-
dc.contributor.authorLin, Zhiwei-
dc.contributor.authorFagan, Jeffrey-
dc.contributor.authorZheng, Ming-
dc.contributor.authorWang, Han-
dc.contributor.authorMitra, Subhasish-
dc.contributor.authorPhilip Wong, H. S.-
dc.contributor.authorRadu, Iuliana-
dc.date.accessioned2023-11-17T08:26:14Z-
dc.date.available2023-11-17T08:26:14Z-
dc.date.issued2023-
dc.identifier.citationDigest of Technical Papers - Symposium on VLSI Technology, 2023, v. 2023-June-
dc.identifier.issn0743-1562-
dc.identifier.urihttp://hdl.handle.net/10722/335476-
dc.description.abstractHigh-performance and scaled transistors on carbon nanotube (CNT) channel are enabled by the quality of device component modules. This paper advances each module by single-CNT control experiments reporting: (1) remarkable n-type contact resistance of 5.1 kΩ/CNT(20.4Ω-μm for 250 CNT/μm) at 20 nm contact length, (2) tunable N-and Pdoping of CNT with dielectric doping, (3) improvement in top-gate dielectric interface to CNT by channel cleaning, (4) demonstration of channel comprised of dense CNT array with reduced bundle density, and (5) analysis of CNT bandgap tradeoffs with variability control strategy. The first component-complete pMOS FET is demonstrated on high-density CNTs with up to 680 μA/μm at -0.7V VDS.-
dc.languageeng-
dc.relation.ispartofDigest of Technical Papers - Symposium on VLSI Technology-
dc.subject1D-
dc.subject2D-
dc.subjectCMOS-
dc.subjectCNT-
dc.subjectlow-dimensional material-
dc.titleBuilding high performance transistors on carbon nanotube channel-
dc.typeConference_Paper-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.23919/VLSITechnologyandCir57934.2023.10185374-
dc.identifier.scopuseid_2-s2.0-85167561481-
dc.identifier.volume2023-June-

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