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- Publisher Website: 10.1109/IEDM45625.2022.10019482
- Scopus: eid_2-s2.0-85147504160
- WOS: WOS:000968800700138
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Conference Paper: Device Variation-Aware Adaptive Quantization for MRAM-based Accurate In-Memory Computing Without On-chip Training
Title | Device Variation-Aware Adaptive Quantization for MRAM-based Accurate In-Memory Computing Without On-chip Training |
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Authors | |
Issue Date | 3-Dec-2022 |
Publisher | IEEE |
Abstract | Hardware-accelerated artificial intelligence with emerging nonvolatile memory such as spin-transfer torque-magneto-resistive random-access memory (STT-MRAM) is pushing both the algorithm and hardware to their design limits. The restrictions for analog-based in-memory computing (IMC) include the device variation, IR drop effect due to low resistance of STT-MRAM and read disturbance in the memory array at the advanced technology node. On-chip hybrid training can recover the inference accuracy but at the cost of many training epochs, reducing the available lifetime for updating cycles needed for on-chip inference. In this work, we show the unique feature of device variations in the foundry STT-MRAM array and propose a software-hardware cross-layer co-design scheme for STT-MRAM IMC. By sensing device level variations, we can leverage them for more conductance levels to adaptively quantize the deep neural networks (DNNs). This device variation-aware adaptive quantization (DVAQ) scheme enables a DNN inference accuracy comparable to on-chip hybrid training without on-chip training. Besides, this DVAQ scheme greatly reduces IR drop effects. Overall, the DVAQ allows one to achieve less than a 1% accuracy drop compared with in-situ training under 40 % device variation/noise without on-chip training in several DNN applications. |
Persistent Identifier | http://hdl.handle.net/10722/340343 |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Xiao, Zhihua | - |
dc.contributor.author | Naik, Vinayak Bharat | - |
dc.contributor.author | Cheung, Shun Kong | - |
dc.contributor.author | Lim, Jia Hao | - |
dc.contributor.author | Kwon, Jae-Hyun | - |
dc.contributor.author | Ren, Zheyu | - |
dc.contributor.author | Wang, Zhongrui | - |
dc.contributor.author | Shao, Qiming | - |
dc.date.accessioned | 2024-03-11T10:43:28Z | - |
dc.date.available | 2024-03-11T10:43:28Z | - |
dc.date.issued | 2022-12-03 | - |
dc.identifier.uri | http://hdl.handle.net/10722/340343 | - |
dc.description.abstract | <p>Hardware-accelerated artificial intelligence with emerging nonvolatile memory such as spin-transfer torque-magneto-resistive random-access memory (STT-MRAM) is pushing both the algorithm and hardware to their design limits. The restrictions for analog-based in-memory computing (IMC) include the device variation, IR drop effect due to low resistance of STT-MRAM and read disturbance in the memory array at the advanced technology node. On-chip hybrid training can recover the inference accuracy but at the cost of many training epochs, reducing the available lifetime for updating cycles needed for on-chip inference. In this work, we show the unique feature of device variations in the foundry STT-MRAM array and propose a software-hardware cross-layer co-design scheme for STT-MRAM IMC. By sensing device level variations, we can leverage them for more conductance levels to adaptively quantize the deep neural networks (DNNs). This device variation-aware adaptive quantization (DVAQ) scheme enables a DNN inference accuracy comparable to on-chip hybrid training without on-chip training. Besides, this DVAQ scheme greatly reduces IR drop effects. Overall, the DVAQ allows one to achieve less than a 1% accuracy drop compared with in-situ training under 40 % device variation/noise without on-chip training in several DNN applications.<br></p> | - |
dc.language | eng | - |
dc.publisher | IEEE | - |
dc.relation.ispartof | 2022 IEEE International Electron Devices Meeting (IEDM) (03/12/2022-07/12/2022, San Francisco, CA, USA) | - |
dc.title | Device Variation-Aware Adaptive Quantization for MRAM-based Accurate In-Memory Computing Without On-chip Training | - |
dc.type | Conference_Paper | - |
dc.identifier.doi | 10.1109/IEDM45625.2022.10019482 | - |
dc.identifier.scopus | eid_2-s2.0-85147504160 | - |
dc.identifier.volume | 2022-December | - |
dc.identifier.spage | 1051 | - |
dc.identifier.epage | 1054 | - |
dc.identifier.isi | WOS:000968800700138 | - |