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- Publisher Website: 10.23919/DATE56975.2023.10136923
- Scopus: eid_2-s2.0-85162722401
- WOS: WOS:001027444200027
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Conference Paper: Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures
Title | Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures |
---|---|
Authors | |
Keywords | application analysis architectural modeling circuit modeling cross-layer design design space explorations device modeling Emerging logic and memory FeFETs RRAM |
Issue Date | 2-Jun-2023 |
Publisher | IEEE |
Abstract | There is great interest in “end-to-end” analysis that captures how innovation at the materials, device, and/or archi-tectural levels will impact figures of merit at the application-level. However, there are numerous combinations of devices and architectures to study, and we must establish systematic ways to accurately explore and cull a vast design space. We aim to capture how innovations at the materials/device-level may ultimately impact figures of merit associated with both existing and emerging technologies that may be employed for either logic and/or memory. We will highlight how collaborations with researchers at these levels of the design hierarchy - as well as efforts to help construct well-calibrated device models - can in-turn support architectural design space explorations that will help to identify the most promising ways to use new technologies to support application-level workloads of interest. For given compute workloads, we can then quantitatively assess the potential benefits of technology-driven architectures to identify the most promising paths forward. Because of the large number of potentially interesting device-architecture combinations, it is of the utmost importance to develop well-calibrated analytical modeling tools to more rapidly assess the potential value of a given (likely heterogeneous) solution. We highlight recent efforts and needs in this space. |
Persistent Identifier | http://hdl.handle.net/10722/340515 |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Niemier, M | - |
dc.contributor.author | Hu, XS | - |
dc.contributor.author | Liu, L | - |
dc.contributor.author | Sharifi, M | - |
dc.contributor.author | O’Connor, Ian | - |
dc.contributor.author | Atienza, David | - |
dc.contributor.author | Ansaloni, Giovanni | - |
dc.contributor.author | Li, Can | - |
dc.contributor.author | Khan, Asif | - |
dc.contributor.author | Ralph, Daniel C | - |
dc.date.accessioned | 2024-03-11T10:45:12Z | - |
dc.date.available | 2024-03-11T10:45:12Z | - |
dc.date.issued | 2023-06-02 | - |
dc.identifier.uri | http://hdl.handle.net/10722/340515 | - |
dc.description.abstract | <p>There is great interest in “end-to-end” analysis that captures how innovation at the materials, device, and/or archi-tectural levels will impact figures of merit at the application-level. However, there are numerous combinations of devices and architectures to study, and we must establish systematic ways to accurately explore and cull a vast design space. We aim to capture how innovations at the materials/device-level may ultimately impact figures of merit associated with both existing and emerging technologies that may be employed for either logic and/or memory. We will highlight how collaborations with researchers at these levels of the design hierarchy - as well as efforts to help construct well-calibrated device models - can in-turn support architectural design space explorations that will help to identify the most promising ways to use new technologies to support application-level workloads of interest. For given compute workloads, we can then quantitatively assess the potential benefits of technology-driven architectures to identify the most promising paths forward. Because of the large number of potentially interesting device-architecture combinations, it is of the utmost importance to develop well-calibrated analytical modeling tools to more rapidly assess the potential value of a given (likely heterogeneous) solution. We highlight recent efforts and needs in this space.<br></p> | - |
dc.language | eng | - |
dc.publisher | IEEE | - |
dc.relation.ispartof | 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) (17/04/2023-19/04/2023, Antwerp) | - |
dc.subject | application analysis | - |
dc.subject | architectural modeling | - |
dc.subject | circuit modeling | - |
dc.subject | cross-layer design | - |
dc.subject | design space explorations | - |
dc.subject | device modeling | - |
dc.subject | Emerging logic and memory | - |
dc.subject | FeFETs | - |
dc.subject | RRAM | - |
dc.title | Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures | - |
dc.type | Conference_Paper | - |
dc.identifier.doi | 10.23919/DATE56975.2023.10136923 | - |
dc.identifier.scopus | eid_2-s2.0-85162722401 | - |
dc.identifier.volume | 2023-April | - |
dc.identifier.isi | WOS:001027444200027 | - |