Vertical GaN Fin JFET: A Power Device with Short Circuit Robustness at Avalanche Breakdown Voltage

Abstract

GaN high-electron-mobility transistors (HEMTs) are known to have no avalanche capability and insufficient short-circuit robustness. Recently, breakthrough avalanche and short-circuit capabilities have been experimentally demonstrated in a vertical GaN fin-channel junction-gate field-effect transistor (Fin-JFET), which shows a good promise for using GaN devices in automotive powertrains and electric grids. In particular, GaN Fin-JFETs demonstrated good short-circuit capability at avalanche breakdown voltage (BVAVA), with a failure-to-open-circuit (FTO) signature. This work presents a comprehensive device physics-based study of the GaN Fin-JFET under short-circuit conditions, particularly at a bus voltage close to BVAVA. Mixed-mode electrothermal TCAD simulations were performed to understand the carrier dynamics, electric field distributions, and temperature profiles in the Fin-JFET under short-circuit and avalanche conditions. The results provide important physical references to understand the unique robustness of the vertical GaN Fin-JFET under the concurrence of short-circuit and avalanche as well as its desirable FTO signature.