Investigation on Physical Origins of Output Capacitance Loss in Cascode GaN HEMTs

Abstract

Output capacitance loss is generated when the output capacitor of a power device is charged and discharged in its OFF state, which ideally should be a lossless process. This loss information is not included in the device datasheet but is crucial for device applications. Some recent work has revealed significant EDISS in GaN high-electron-mobility transistors (HEMTs), which compromise their performance in high-frequency soft-switching converters. Among various GaN devices, the cascode GaN HEMT was reported to show the largest EDISS, but its physical origin is unknown. This work investigates several possible physical origins such as the EDISS of GaN HEMT and the Si avalanche loss. The EDISS of two cascode GaN HEMTs, one with and the other without an additional capacitor in parallel with the Si MOSFET, are characterized. Three components of EDISS in cascode GaN HEMTs are quantitatively separated: a) Si avalanche loss, b) GaN HEMT's inherent EDISS, and c) additional loss due to the interaction between Si MOSFET and GaN HEMT when the Si MOSFET avalanches. At high voltage, component c) is revealed to dominate. By eliminating the Si avalanche, the EDISS of cascode GaN HEMTs can be reduced by up to 75%. These results provide new physical insights and manifest an effective way to reduce EDISS in casco de GaN HEMTs, which significantly boost its performance in soft- switching applications.