Minimizing Output Capacitance Loss in GaN Power HEMT

Abstract

Output capacitance (COSS) loss (EDISS) is produced when the COSS of a power device undergoes a cycle of charging and discharging, which ideally should be a lossless process. This nonideal phenomenon has been recently revealed to be a critical loss for wide-bandgap devices in high-frequency, soft-switching applications. Despite many studies on its characterizations and physical origins, the reduction of EDISS, particularly through an approach applicable to circuit application instead of relying on physical device design, has seldom been reported. In this article, we found that the EDISS of GaN-on-Si high electron mobility transistors (HEMTs) can be significantly reduced by tuning the bias of Si substrate (VSub) in dynamic switching. By connecting the substrate to the source or drain via the selected capacitance, VSub can be modulated to dynamically follow either the drain-to-source bias (VDS) or a particular portion of VDS in switching. Characterizations of a 650 V GaN HEMT with different substrate connections reveal that its EDISS maximizes at VSub = VDS and minimizes at VSub = 0.5VDS. Compared to the conventional substrate-to-source shorted connection, the EDISS at VSub = 0.5VDS is reduced by up to 86%, and the ratio between EDISS and the stored energy in COSS can be reduced from 14.6% to 2.2%. These results unveil a new, easy-to-implement approach to minimize the inherent COSS loss of GaN HEMTs in practical applications.