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Article: Binary Weight Multi-Bit Activation Quantization for Compute-in-Memory CNN Accelerators

TitleBinary Weight Multi-Bit Activation Quantization for Compute-in-Memory CNN Accelerators
Authors
KeywordsCompute-in-Memory
FeFET
Model Qquantization
RRAM
SRAM
Issue Date1-Jan-2025
PublisherInstitute of Electrical and Electronics Engineers
Citation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025 How to Cite?
AbstractCompute-in-memory (CIM) accelerators have emerged as a promising way for enhancing the energy efficiency of convolutional neural networks (CNNs). Deploying CNNs on CIM platforms generally requires quantization of network weights and activations to meet hardware constraints. However, existing approaches either prioritize hardware efficiency with binary weight and activation quantization at the cost of accuracy, or utilize multi-bit weights and activations for greater accuracy but limited efficiency. In this paper, we introduce a novel binary weight multi-bit activation (BWMA) method for CNNs on CIM-based accelerators. Our contributions include: deriving closed-form solutions for weight quantization in each layer, significantly improving the representational capabilities of binarized weights; and developing a differentiable function for activation quantization, approximating the ideal multi-bit function while bypassing the extensive search for optimal settings. Through comprehensive experiments on CIFAR-10 and ImageNet datasets, we show that BWMA achieves notable accuracy improvements over existing methods, registering gains of 1.44%-5.46% and 0.35%-5.37% on respective datasets. Moreover, hardware simulation results indicate that 4-bit activation quantization strikes the optimal balance between hardware cost and model performance.
Persistent Identifierhttp://hdl.handle.net/10722/362535
ISSN
2023 Impact Factor: 2.7
2023 SCImago Journal Rankings: 0.957

 

DC FieldValueLanguage
dc.contributor.authorZhou, Wenyong-
dc.contributor.authorLiu, Zhengwu-
dc.contributor.authorRen, Yuan-
dc.contributor.authorWong, Ngai-
dc.date.accessioned2025-09-26T00:35:59Z-
dc.date.available2025-09-26T00:35:59Z-
dc.date.issued2025-01-01-
dc.identifier.citationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025-
dc.identifier.issn0278-0070-
dc.identifier.urihttp://hdl.handle.net/10722/362535-
dc.description.abstractCompute-in-memory (CIM) accelerators have emerged as a promising way for enhancing the energy efficiency of convolutional neural networks (CNNs). Deploying CNNs on CIM platforms generally requires quantization of network weights and activations to meet hardware constraints. However, existing approaches either prioritize hardware efficiency with binary weight and activation quantization at the cost of accuracy, or utilize multi-bit weights and activations for greater accuracy but limited efficiency. In this paper, we introduce a novel binary weight multi-bit activation (BWMA) method for CNNs on CIM-based accelerators. Our contributions include: deriving closed-form solutions for weight quantization in each layer, significantly improving the representational capabilities of binarized weights; and developing a differentiable function for activation quantization, approximating the ideal multi-bit function while bypassing the extensive search for optimal settings. Through comprehensive experiments on CIFAR-10 and ImageNet datasets, we show that BWMA achieves notable accuracy improvements over existing methods, registering gains of 1.44%-5.46% and 0.35%-5.37% on respective datasets. Moreover, hardware simulation results indicate that 4-bit activation quantization strikes the optimal balance between hardware cost and model performance.-
dc.languageeng-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.relation.ispartofIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems-
dc.subjectCompute-in-Memory-
dc.subjectFeFET-
dc.subjectModel Qquantization-
dc.subjectRRAM-
dc.subjectSRAM-
dc.titleBinary Weight Multi-Bit Activation Quantization for Compute-in-Memory CNN Accelerators -
dc.typeArticle-
dc.identifier.doi10.1109/TCAD.2025.3595830-
dc.identifier.scopuseid_2-s2.0-105013344940-
dc.identifier.eissn1937-4151-
dc.identifier.issnl0278-0070-

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