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Article: Parallelization methodology for video coding - an implementation on the TMS320C80
Title | Parallelization methodology for video coding - an implementation on the TMS320C80 |
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Authors | |
Issue Date | 2000 |
Publisher | IEEE. |
Citation | Ieee Transactions On Circuits And Systems For Video Technology, 2000, v. 10 n. 8, p. 1413-1425 How to Cite? |
Abstract | This paper presents a parallelization methodology for video coding based on the philosophy of hiding as much communications by computation as possible. It models the task/data size, processor cache capacity, and communication contention, through a systematic decomposition and scheduling approach. With the aid of Petri-nets and task graphs for representation and analysis, it employs a triple buffering scheme to enable the functions of frame capture, management, and coding to be performed in parallel. The theoretical speedup analysis indicates that this method offers excellent communication hiding, resulting in system efficiency well above 90%. To prove its practicality, a H.261 video encoder has been implemented on a TMS320C80 system using the method. Its performance was measured, from which the speedup and efficiency figures were calculated. The only difference detected between the theoretical and measured data is the program control overhead that has not been accounted for in the theoretical model. Even with this, the measured speedup of the H.261 is 3.67 and 3.76 on four parallel processors (PPs) for QCIF and 352 × 240 video, respectively, which correspond to frame rate of 30.7 and 9.25 frames per second, and system efficiency of 91.8% and 94%, respectively. This method is particularly efficient for platforms with small number of parallel processors. |
Persistent Identifier | http://hdl.handle.net/10722/42876 |
ISSN | 2023 Impact Factor: 8.3 2023 SCImago Journal Rankings: 2.299 |
ISI Accession Number ID | |
References |
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Leung, KK | en_HK |
dc.contributor.author | Yung, NHC | en_HK |
dc.contributor.author | Cheung, PYS | en_HK |
dc.date.accessioned | 2007-03-23T04:33:52Z | - |
dc.date.available | 2007-03-23T04:33:52Z | - |
dc.date.issued | 2000 | en_HK |
dc.identifier.citation | Ieee Transactions On Circuits And Systems For Video Technology, 2000, v. 10 n. 8, p. 1413-1425 | en_HK |
dc.identifier.issn | 1051-8215 | en_HK |
dc.identifier.uri | http://hdl.handle.net/10722/42876 | - |
dc.description.abstract | This paper presents a parallelization methodology for video coding based on the philosophy of hiding as much communications by computation as possible. It models the task/data size, processor cache capacity, and communication contention, through a systematic decomposition and scheduling approach. With the aid of Petri-nets and task graphs for representation and analysis, it employs a triple buffering scheme to enable the functions of frame capture, management, and coding to be performed in parallel. The theoretical speedup analysis indicates that this method offers excellent communication hiding, resulting in system efficiency well above 90%. To prove its practicality, a H.261 video encoder has been implemented on a TMS320C80 system using the method. Its performance was measured, from which the speedup and efficiency figures were calculated. The only difference detected between the theoretical and measured data is the program control overhead that has not been accounted for in the theoretical model. Even with this, the measured speedup of the H.261 is 3.67 and 3.76 on four parallel processors (PPs) for QCIF and 352 × 240 video, respectively, which correspond to frame rate of 30.7 and 9.25 frames per second, and system efficiency of 91.8% and 94%, respectively. This method is particularly efficient for platforms with small number of parallel processors. | en_HK |
dc.format.extent | 258898 bytes | - |
dc.format.extent | 26112 bytes | - |
dc.format.extent | 5183 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.format.mimetype | application/msword | - |
dc.format.mimetype | text/plain | - |
dc.language | eng | en_HK |
dc.publisher | IEEE. | en_HK |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems for Video Technology | en_HK |
dc.rights | ©2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | - |
dc.title | Parallelization methodology for video coding - an implementation on the TMS320C80 | en_HK |
dc.type | Article | en_HK |
dc.identifier.openurl | http://library.hku.hk:4550/resserv?sid=HKU:IR&issn=1051-8215&volume=10&issue=8&spage=1413&epage=1425&date=2000&atitle=Parallelization+methodology+for+video+coding-an+implementation+on+the+TMS320C80 | en_HK |
dc.identifier.email | Yung, NHC:nyung@eee.hku.hk | en_HK |
dc.identifier.email | Cheung, PYS:paul.cheung@hku.hk | en_HK |
dc.identifier.authority | Yung, NHC=rp00226 | en_HK |
dc.identifier.authority | Cheung, PYS=rp00077 | en_HK |
dc.description.nature | published_or_final_version | en_HK |
dc.identifier.doi | 10.1109/76.889035 | en_HK |
dc.identifier.scopus | eid_2-s2.0-0034507010 | en_HK |
dc.identifier.hkuros | 60586 | - |
dc.relation.references | http://www.scopus.com/mlt/select.url?eid=2-s2.0-0034507010&selection=ref&src=s&origin=recordpage | en_HK |
dc.identifier.volume | 10 | en_HK |
dc.identifier.issue | 8 | en_HK |
dc.identifier.spage | 1413 | en_HK |
dc.identifier.epage | 1425 | en_HK |
dc.identifier.isi | WOS:000165834300006 | - |
dc.publisher.place | United States | en_HK |
dc.identifier.scopusauthorid | Leung, KK=35779695300 | en_HK |
dc.identifier.scopusauthorid | Yung, NHC=7003473369 | en_HK |
dc.identifier.scopusauthorid | Cheung, PYS=7202595335 | en_HK |
dc.identifier.issnl | 1051-8215 | - |