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Conference Paper: Design for self-checking and self-timed datapath
| Title | Design for self-checking and self-timed datapath |
|---|---|
| Authors | |
| Keywords | Self-checking aasynchronous datapath differential cascode voltage switch logic dynamic circuits |
| Issue Date | 2003 |
| Publisher | IEEE. |
| Citation | The 21st IEEE - VLSI Test Symposium Proceedings, California, USA, 27 April - 1 May 2003, p. 417-422 How to Cite? |
| Abstract | This work examines the inherent self-checking property of a latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic (DCVSL). Consequently, a highly efficient self-checking (SC) dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve self-checking. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design. |
| Persistent Identifier | http://hdl.handle.net/10722/46402 |
| ISSN |
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yang, JL | en_HK |
| dc.contributor.author | Choy, CS | en_HK |
| dc.contributor.author | Chan, CF | en_HK |
| dc.contributor.author | Pun, KP | en_HK |
| dc.date.accessioned | 2007-10-30T06:49:05Z | - |
| dc.date.available | 2007-10-30T06:49:05Z | - |
| dc.date.issued | 2003 | en_HK |
| dc.identifier.citation | The 21st IEEE - VLSI Test Symposium Proceedings, California, USA, 27 April - 1 May 2003, p. 417-422 | en_HK |
| dc.identifier.issn | 1093-0167 | en_HK |
| dc.identifier.uri | http://hdl.handle.net/10722/46402 | - |
| dc.description.abstract | This work examines the inherent self-checking property of a latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic (DCVSL). Consequently, a highly efficient self-checking (SC) dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve self-checking. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design. | en_HK |
| dc.format.extent | 616950 bytes | - |
| dc.format.extent | 1735 bytes | - |
| dc.format.mimetype | application/pdf | - |
| dc.format.mimetype | text/plain | - |
| dc.language | eng | en_HK |
| dc.publisher | IEEE. | en_HK |
| dc.relation.ispartof | Proceedings of the 21st IEEE VLSI Test Symposium | - |
| dc.rights | ©2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | - |
| dc.subject | Self-checking | en_HK |
| dc.subject | aasynchronous datapath | en_HK |
| dc.subject | differential cascode voltage switch logic | en_HK |
| dc.subject | dynamic circuits | en_HK |
| dc.title | Design for self-checking and self-timed datapath | en_HK |
| dc.type | Conference_Paper | en_HK |
| dc.identifier.openurl | http://library.hku.hk:4550/resserv?sid=HKU:IR&issn=1093-0167&volume=&spage=417&epage=422&date=2003&atitle=Design+for+self-checking+and+self-timed+datapath | en_HK |
| dc.description.nature | published_or_final_version | en_HK |
| dc.identifier.doi | 10.1109/VTEST.2003.1197683 | - |
| dc.identifier.scopus | eid_2-s2.0-28444482181 | - |
| dc.identifier.hkuros | 83051 | - |
| dc.identifier.issnl | 1093-0167 | - |