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Article: Quad-level bit-stream adders and multipliers with efficient FPGA implementation
Title | Quad-level bit-stream adders and multipliers with efficient FPGA implementation |
---|---|
Authors | |
Issue Date | 2008 |
Publisher | The Institution of Engineering and Technology. The Journal's web site is located at http://www.ieedl.org/EL |
Citation | Electronics Letters, 2008, v. 44 n. 12, p. 722-724 How to Cite? |
Abstract | Novel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (>76 hardware savings) and faster (>93 higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six-input look-up tables. © 2008 The Institution of Engineering and Technology. |
Persistent Identifier | http://hdl.handle.net/10722/73707 |
ISSN | 2023 Impact Factor: 0.7 2023 SCImago Journal Rankings: 0.323 |
ISI Accession Number ID | |
References |
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ng, CW | en_HK |
dc.contributor.author | Wong, N | en_HK |
dc.contributor.author | Ng, TS | en_HK |
dc.date.accessioned | 2010-09-06T06:53:59Z | - |
dc.date.available | 2010-09-06T06:53:59Z | - |
dc.date.issued | 2008 | en_HK |
dc.identifier.citation | Electronics Letters, 2008, v. 44 n. 12, p. 722-724 | en_HK |
dc.identifier.issn | 0013-5194 | en_HK |
dc.identifier.uri | http://hdl.handle.net/10722/73707 | - |
dc.description.abstract | Novel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (>76 hardware savings) and faster (>93 higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six-input look-up tables. © 2008 The Institution of Engineering and Technology. | en_HK |
dc.language | eng | en_HK |
dc.publisher | The Institution of Engineering and Technology. The Journal's web site is located at http://www.ieedl.org/EL | en_HK |
dc.relation.ispartof | Electronics Letters | en_HK |
dc.title | Quad-level bit-stream adders and multipliers with efficient FPGA implementation | en_HK |
dc.type | Article | en_HK |
dc.identifier.email | Wong, N:nwong@eee.hku.hk | en_HK |
dc.identifier.email | Ng, TS:tsng@eee.hku.hk | en_HK |
dc.identifier.authority | Wong, N=rp00190 | en_HK |
dc.identifier.authority | Ng, TS=rp00159 | en_HK |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1049/el:20080547 | en_HK |
dc.identifier.scopus | eid_2-s2.0-44649162081 | en_HK |
dc.identifier.hkuros | 152259 | en_HK |
dc.relation.references | http://www.scopus.com/mlt/select.url?eid=2-s2.0-44649162081&selection=ref&src=s&origin=recordpage | en_HK |
dc.identifier.volume | 44 | en_HK |
dc.identifier.issue | 12 | en_HK |
dc.identifier.spage | 722 | en_HK |
dc.identifier.epage | 724 | en_HK |
dc.identifier.isi | WOS:000256813200012 | - |
dc.publisher.place | United Kingdom | en_HK |
dc.identifier.scopusauthorid | Ng, CW=36747471300 | en_HK |
dc.identifier.scopusauthorid | Wong, N=35235551600 | en_HK |
dc.identifier.scopusauthorid | Ng, TS=7402229975 | en_HK |
dc.identifier.issnl | 0013-5194 | - |