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Article: Efficient FPGA implementation of bit-stream multipliers

TitleEfficient FPGA implementation of bit-stream multipliers
Authors
Ng, CWWong, NNg, TS
Issue Date2007
PublisherThe Institution of Engineering and Technology. The Journal's web site is located at http://www.ieedl.org/EL
Citation
Electronics Letters, 2007, v. 43 n. 9, p. 496-497 How to Cite?
DOI: http://dx.doi.org/10.1049/el:20070293
AbstractA four-input adder structure for the FPGA implementation of a sigma-delta bit-stream multiplier is proposed. Conventional bit-stream multiplier implementations involve two-input adder circuits. It is shown that the four-input adder structure is more resource-efficient (over 40% hardware savings) and faster (over 20% higher clock frequency) when implemented using state-of-the-art FPGA architecture featuring six-input look-up tables. © The Institution of Engineering and Technology 2007.
Persistent Identifierhttp://hdl.handle.net/10722/73911
ISSN
0013-5194
2023 Impact Factor: 0.7
2023 SCImago Journal Rankings: 0.323
ISI Accession Number ID
WOS:000246875600008
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorNg, CWen_HK
dc.contributor.authorWong, Nen_HK
dc.contributor.authorNg, TSen_HK
dc.date.accessioned2010-09-06T06:55:57Z-
dc.date.available2010-09-06T06:55:57Z-
dc.date.issued2007en_HK
dc.identifier.citationElectronics Letters, 2007, v. 43 n. 9, p. 496-497en_HK
dc.identifier.issn0013-5194en_HK
dc.identifier.urihttp://hdl.handle.net/10722/73911-
dc.description.abstractA four-input adder structure for the FPGA implementation of a sigma-delta bit-stream multiplier is proposed. Conventional bit-stream multiplier implementations involve two-input adder circuits. It is shown that the four-input adder structure is more resource-efficient (over 40% hardware savings) and faster (over 20% higher clock frequency) when implemented using state-of-the-art FPGA architecture featuring six-input look-up tables. © The Institution of Engineering and Technology 2007.en_HK
dc.languageengen_HK
dc.publisherThe Institution of Engineering and Technology. The Journal's web site is located at http://www.ieedl.org/ELen_HK
dc.relation.ispartofElectronics Lettersen_HK
dc.titleEfficient FPGA implementation of bit-stream multipliersen_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=0013-5194&volume=43&spage=496&epage=497&date=2007&atitle=Efficient+FPGA+Implementation+of+Bit-Stream+Multipliersen_HK
dc.identifier.emailWong, N:nwong@eee.hku.hken_HK
dc.identifier.emailNg, TS:tsng@eee.hku.hken_HK
dc.identifier.authorityWong, N=rp00190en_HK
dc.identifier.authorityNg, TS=rp00159en_HK
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1049/el:20070293en_HK
dc.identifier.scopuseid_2-s2.0-34247567904en_HK
dc.identifier.hkuros133549en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-34247567904&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume43en_HK
dc.identifier.issue9en_HK
dc.identifier.spage496en_HK
dc.identifier.epage497en_HK
dc.identifier.isiWOS:000246875600008-
dc.publisher.placeUnited Kingdomen_HK
dc.identifier.scopusauthoridNg, CW=36747471300en_HK
dc.identifier.scopusauthoridWong, N=35235551600en_HK
dc.identifier.scopusauthoridNg, TS=7402229975en_HK
dc.identifier.citeulike3501377-
dc.identifier.issnl0013-5194-

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