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- Publisher Website: 10.1109/HPSR.2007.4281253
- Scopus: eid_2-s2.0-47649101726
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Conference Paper: Load-balanced three-stage switch architecture
Title | Load-balanced three-stage switch architecture |
---|---|
Authors | |
Keywords | Load-balanced switch Three-stage switch Two-stage switch |
Issue Date | 2007 |
Publisher | IEEE. |
Citation | 2007 Ieee Workshop On High Performance Switching And Routing, Hpsr, 2007, p. 1-6 How to Cite? |
Abstract | A load-balanced two-stage switch is scalable and can provide close to 100% throughput. Its major problem is that packets can be mis-sequenced when they arrive at output ports. In a recent work [16], the packet mis-sequencing problem is elegantly solved by a feedback-based two-stage switch architecture. In this paper, we extend the feedback-based switch architecture from two-stage to three-stage to further cut down packet delay. The idea is to map the heavy flows to experience less middle-stage port delay using the switch fabric in the third stage. We show that the resulting three-stage architecture also ensures in-order packet delivery and close to 100% throughput. To identity heavy flows, a simple and practical traffic matrix estimation algorithm is also proposed. As compared with the original feedback-based two-stage switch architecture, the three-stage switch can cut down the delay performance by as large as 43.4% for a 32x32 switch under a hot-spot traffic pattern with input load at p=0.95. For random uniform traffic, the saving in delay is about 8%. ©2007 IEEE. |
Persistent Identifier | http://hdl.handle.net/10722/98948 |
References |
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hu, B | en_HK |
dc.contributor.author | Yeung, KL | en_HK |
dc.date.accessioned | 2010-09-25T18:09:17Z | - |
dc.date.available | 2010-09-25T18:09:17Z | - |
dc.date.issued | 2007 | en_HK |
dc.identifier.citation | 2007 Ieee Workshop On High Performance Switching And Routing, Hpsr, 2007, p. 1-6 | en_HK |
dc.identifier.uri | http://hdl.handle.net/10722/98948 | - |
dc.description.abstract | A load-balanced two-stage switch is scalable and can provide close to 100% throughput. Its major problem is that packets can be mis-sequenced when they arrive at output ports. In a recent work [16], the packet mis-sequencing problem is elegantly solved by a feedback-based two-stage switch architecture. In this paper, we extend the feedback-based switch architecture from two-stage to three-stage to further cut down packet delay. The idea is to map the heavy flows to experience less middle-stage port delay using the switch fabric in the third stage. We show that the resulting three-stage architecture also ensures in-order packet delivery and close to 100% throughput. To identity heavy flows, a simple and practical traffic matrix estimation algorithm is also proposed. As compared with the original feedback-based two-stage switch architecture, the three-stage switch can cut down the delay performance by as large as 43.4% for a 32x32 switch under a hot-spot traffic pattern with input load at p=0.95. For random uniform traffic, the saving in delay is about 8%. ©2007 IEEE. | en_HK |
dc.language | eng | en_HK |
dc.publisher | IEEE. | en_HK |
dc.relation.ispartof | 2007 IEEE Workshop on High Performance Switching and Routing, HPSR | en_HK |
dc.subject | Load-balanced switch | en_HK |
dc.subject | Three-stage switch | en_HK |
dc.subject | Two-stage switch | en_HK |
dc.title | Load-balanced three-stage switch architecture | en_HK |
dc.type | Conference_Paper | en_HK |
dc.identifier.email | Yeung, KL:kyeung@eee.hku.hk | en_HK |
dc.identifier.authority | Yeung, KL=rp00204 | en_HK |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1109/HPSR.2007.4281253 | en_HK |
dc.identifier.scopus | eid_2-s2.0-47649101726 | en_HK |
dc.identifier.hkuros | 133927 | en_HK |
dc.relation.references | http://www.scopus.com/mlt/select.url?eid=2-s2.0-47649101726&selection=ref&src=s&origin=recordpage | en_HK |
dc.identifier.spage | 1 | en_HK |
dc.identifier.epage | 6 | en_HK |
dc.identifier.scopusauthorid | Hu, B=36617158500 | en_HK |
dc.identifier.scopusauthorid | Yeung, KL=7202424908 | en_HK |