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Conference Paper: DSP48E efficient floating point multiplier architectures on FPGA

TitleDSP48E efficient floating point multiplier architectures on FPGA
Authors
Issue Date2017
PublisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000799
Citation
Proceedings of the 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), Hyderabad, India, 7-11 January 2017, p. 1-6 How to Cite?
Persistent Identifierhttp://hdl.handle.net/10722/247793

 

DC FieldValueLanguage
dc.contributor.authorJaiswal, MK-
dc.contributor.authorSo, HKH-
dc.date.accessioned2017-10-18T08:32:44Z-
dc.date.available2017-10-18T08:32:44Z-
dc.date.issued2017-
dc.identifier.citationProceedings of the 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), Hyderabad, India, 7-11 January 2017, p. 1-6-
dc.identifier.urihttp://hdl.handle.net/10722/247793-
dc.languageeng-
dc.publisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000799-
dc.relation.ispartofInternational Conference on VLSI Design & International Conference on Embedded Systems (VLSID)-
dc.rights©2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.titleDSP48E efficient floating point multiplier architectures on FPGA-
dc.typeConference_Paper-
dc.identifier.emailJaiswal, MK: manishkj@hku.hk-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturepostprint-
dc.identifier.doi10.1109/ICVD.2017.7913322-
dc.identifier.hkuros280271-
dc.identifier.spage1-
dc.identifier.epage6-
dc.publisher.placeUnited States-

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