Browsing by Author Li, Kai Shin

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Showing results 1 to 8 of 8
TitleAuthor(s)Issue Date
 
A numerical study of Si-TMD contact with n/p type operation and interface barrier reduction for sub-5 nm monolayer MoS<inf>2</inf> FET
Proceeding/Conference:International Electron Devices Meeting (IEDM)
Tang, Ying TsanLi, Kai ShinLi, Lain JongLi, Ming YangLin, Chang HsienChen, Yi JuChen, Chun ChiSu, Chuan JungWu, Bo WeiWu, Cheng SanChen, Min ChengShieh, Jia MinYeh, Wen KuanSu, Po ChengWang, TahuiYang, Fu LiangHu, Chenming
2017
 
Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS<inf>2</inf> Channel Directly Grown on SiO<inf>x</inf>/Si Substrates Using Area-Selective CVD Technology
Journal:IEEE Transactions on Electron Devices
Chung, Yun YanShieh, Jia MinSu, Sheng KaiChiang, Hung LiChen, Tzu ChiangLi, Lain JongWong, H. S.PhilipJian, Wen BinChien, Chao HsinLu, Kuan ChengCheng, Chao ChingLi, Ming YangLin, Chao TingLi, Chi FengChen, Jyun HongLai, Tung YenLi, Kai Shin
2019
 
Effective N-methyl-2-pyrrolidone wet cleaning for fabricating high-performance monolayer MoS<inf>2</inf> transistors
Journal:Nano Research
Chen, Po ChunLin, Chih PinHong, Chuan JieYang, Chih HaoLin, Yun YanLi, Ming YangLi, Lain JongYu, Tung YuanSu, Chun JungLi, Kai ShinZhong, Yuan LiangHou, Tuo HungLan, Yann Wen
2019
 
First demonstration of 40-nm channel length top-gate WS<inf>2</inf> pFET using channel area-selective CVD growth directly on SiO<inf>x</inf>/Si substrate
Proceeding/Conference:Digest of Technical Papers - Symposium on VLSI Technology
Cheng, Chao ChingChung, Yun YanLi, Uing YangLin, Chao TingLi, Chi FengChen, Jyun HongLai, Tung YenLi, Kai ShinShieh, Jia MinSu, Sheng KaiChiang, Hung LiChen, Tzu ChiangLi, Lain JongWong, H. S.PhilipChien, Chao Hsin
2019
 
MoS<inf>2</inf> U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS<inf>2</inf> availability
Proceeding/Conference:Digest of Technical Papers - Symposium on VLSI Technology
Li, Kai ShinWu, Bo WeiLi, Lain JongLi, Ming YangCheng, Chia Chin KevinHsu, Cho LunLin, Chang HsienChen, Yi JuChen, Chun ChiWu, Chien TingChen, Min ChengShieh, Jia MinYeh, Wen KuanChueh, Yu LunYang, Fu LiangHu, Chenming
2016
 
Nonvolatile molecular memory with the multilevel states based on MoS<inf>2</inf> nanochannel field effect transistor through tuning gate voltage to control molecular configurations
Journal:Nanotechnology
Lan, Yann WenHong, Chuan JieChen, Po ChunLin, Yun YanYang, Chih HaoChu, Chia JungLi, Ming YangLi, Lain JongSu, Chun JungWu, Bo WeiHou, Tuo HungLi, Kai ShinZhong, Yuan Liang
2020
 
Scalable fabrication of a complementary logic inverter based on MoS<inf>2</inf> fin-shaped field effect transistors
Journal:Nanoscale Horizons
Lan, Yann WenChen, Po ChunLin, Yun YanLi, Ming YangLi, Lain JongTu, Yu LingYang, Fu LiangChen, Min ChengLi, Kai Shin
2019
 
TMD FinFET with 4 nm thin body and back gate control for future low power technology
Proceeding/Conference:International Electron Devices Meeting (IEDM)
Chen, Min ChengLi, Kai ShinLi, Lain JongLu, Ang YuLi, Ming YangChang, Yung HuangLin, Chang HsienChen, Yi JuHou, Yun FangChen, Chun ChiWu, Bo WeiWu, Cheng SanYang, IvyLee, Yao JenShieh, Jia MinYeh, Wen KuanShih, Jyun HongSu, Po ChengSachid, Angada B.Wang, TahuiYang, Fu LiangHu, Chenming
2015
Showing results 1 to 8 of 8