Browsing by Author Jaiswal, MK

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TitleAuthor(s)Issue Date
 
An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division
Journal:Circuits, Systems, and Signal Processing
Jaiswal, MKSo, HKH
2018
 
Architecture for dual-mode quadruple precision floating point adder
Proceeding/Conference:IEEE Computer Society Annual Symposium on VLSI
Jaiswal, MKBogaraju, SVSo, HKH
2015
 
Architecture for quadruple precision floating point division with multi-precision support
Proceeding/Conference:International Conference on Application-Specific Systems, Architecture and Processors (ASAP) Proceedings
Jaiswal, MKSo, HKH
2016
 
Architecture Generator for Type-3 Unum Posit Adder/Subtractor
Proceeding/Conference:2018 IEEE International Symposium on Circuits and Systems (ISCAS)
Jaiswal, MKSo, HKH
2018
 
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division
Journal:IEEE Transactions on Circuits and Systems I: Regular Papers
Jaiswal, MKSo, HKH
2017
 
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support
Journal:Microelectronics Journal
Jaiswal, MKCheung, RCC
2013
 
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division
Proceeding/Conference:IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Jaiswal, MKCheung, RCCBalakrishnan, MPaul, K
2014
 
Configurable Architectures For Multi-mode Floating Point Adders
Journal:IEEE Transactions On Circuits And Systems I: Regular Papers
Jaiswal, MKBogaraju, SVSo, HKHBalakrishnan, MPaul, KCheung, RCC
2015
 
Design of quadruple precision multiplier architectures with SIMD single and double precision support
Journal:Integration: the VLSI journal
Jaiswal, MKSo, HKH
2019
 
Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM)
Proceeding/Conference:International Conference on Field Programmable Logic and Applications
Ullah, ZJaiswal, MKCheung, RCC
2013
 
DSP48E efficient floating point multiplier architectures on FPGA
Proceeding/Conference:International Conference on VLSI Design & International Conference on Embedded Systems (VLSID)
Jaiswal, MKSo, HKH
2017
 
Dual-Mode Double Precision / Two-Parallel Single Precision Floating Point Multiplier Architecture
Proceeding/Conference:IFIP International Conference on Very Large Scale Integration (VLSI-SoC)
Jaiswal, MKSo, HKH
2015
 
Dual-mode double precision division architecture
Proceeding/Conference:International Midwest Symposium on Circuits and Systems Conference Proceedings
Jaiswal, MKSo, HKH
2016
 
E-TCAM: An Efficient SRAM-Based Architecture for TCAM
Journal:Circuits, Systems, and Signal Processing
Ullah, ZJaiswal, MKCheung, RCC
2014
 
Fast Content Updating Algorithm For An Sram-based Tcam On Fpga
Journal:IEEE Embedded Systems Letters
Farkhanda, SUllah, ZJaiswal, MK
2018
 
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform
Proceeding/Conference:IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig)
Ng, HCWang, MChung, BMFBogaraju, SVJaiswal, MKHo, SMHTsia, KKMShum, HCSo, HKH
2016
 
PACoGen: A Hardware Posit Arithmetic Core Generator
Journal:IEEE Access
Jaiswal, MKSo, HKH
2019
 
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA
Proceeding/Conference:IEEE International Conference on FieId-Programmable Technology Proceedings
Wang, MNg, HCChung, BMFBogaraju, SVJaiswal, MKTsia, KKMShum, HCSo, HKH
2016
 
Series Expansion based Efficient Architectures for Double Precision Floating Point Division
Journal:Circuits, Systems, and Signal Processing
Jaiswal, MKCheung, RCCBalakrishnan, MPaul, K
2014
 
Taylor series based architecture for Quadruple Precision Floating Point Division
Proceeding/Conference:IEEE Computer Society Annual Symposium on VLSI
Jaiswal, MKSo, HKH
2016
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